Delay Monitor Circuit for Sensitive Nodes in SRAM-Based FPGA

2018/07/30 by Mostafa Darvishi, Darvishi, Mostafa, Yves Audet +3
Computer Science · Physics and Astronomy · #FOS: Computer and information sciences #FOS: Physical sciences #Hardware Architecture (cs.AR) #Instrumentation and Detectors (physics.ins-det) #Space Physics (physics.space-ph) #cs.AR #physics.ins-det #physics.space-ph

paper · pdf · doi:10.48550/arxiv.1807.11311

6 Figures, 5 pages, 1 table

arxiv created 2018/07/30 · arxiv updated 2018/07/31

Abstract

This paper presents a novel monitor circuit architecture and experiments performed for detection of extra combinational delays in a high frequency SRAM-Based FPGA on delay sensitive nodes due to transient ionizing radiation.

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