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A handy systematic method for data hazards detection in an instruction set of a pipelined microprocessor

2012/03/04 by Ahmed M. Mahran, Mahran, Ahmed M. · 1 voice
Computer Science · Engineering · #Embedded Systems Design Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Radiation Effects in Electronics #Security and Verification in Computing #cs.AR

paper · pdf · doi:10.48550/arxiv.1203.0787

7 pages, 10 figures, 9 tables

arxiv created 2012/03/04 · openalex publication_date 2012/03/04 · arxiv published 2012/03/04 · arxiv updated 2012/03/04 · openalex created_date 2016/06/24 · openalex updated_date 2026/07/28

Abstract

It is intended in this document to introduce a handy systematic method for enumerating all possible data dependency cases that could occur between any two instructions that might happen to be processed at the same time at different stages of the pipeline. Given instructions of the instruction set, specific information about operands of each instruction and when an instruction reads or writes data, the method could be used to enumerate all possible data hazard cases and to determine whether forwarding or stalling is suitable for resolving each case.

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