2019/12/06 by Zehui Chen, Lara Dolecek, Chen, Zehui +1
Engineering · #Advanced Memory and Neural Computing #FOS: Electrical engineering #Ferroelectric and Negative Capacitance Devices #Semiconductor materials and devices #Systems and Control (eess.SY) #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.1912.02963
openalex publication_date 2019/12/06 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Crossbar resistive memory with 1 Selector 1 Resistor (1S1R) structure is attractive for low-cost and high-density nonvolatile memory applications. As technology scales down to the single-nm regime, the increasing resistivity of wordline/bitline becomes a limiting factor to device reliability. This paper presents write/read communication channels while considering the line resistance and device variabilities by statistically relating the degraded write/read margins and the channel parameters. Binary asymmetric channel (BAC) models are proposed for the write/read operations. Simulations based on these models suggest that the bit-error rate of devices are highly non-uniform across the memory array. These models provide quantitative tools for evaluating the trade-offs between memory reliability and design parameters, such as array size, technology nodes, and aspect ratio, and also for designing coding-theoretic solutions that would be most effective for crossbar memory.