2021/07/28 by Nick Brown, Brown, Nick
Computer Science · #Advanced Data Storage Technologies #Distributed #Embedded Systems Design Techniques #FOS: Computer and information sciences #Mathematical Software (cs.MS) #Parallel #Parallel Computing and Optimization Techniques #and Cluster Computing (cs.DC)
paper · pdf · doi:10.48550/arxiv.2107.13500
openalex publication_date 2021/07/28 · openalex created_date 2022/07/25 · openalex updated_date 2026/07/28
Reconfigurable architectures, such as FPGAs, enable the execution of code at\nthe electronics level, avoiding the assumptions imposed by the general purpose\nblack-box micro-architectures of CPUs and GPUs. Such tailored execution can\nresult in increased performance and power efficiency, and as the HPC community\nmoves towards exascale an important question is the role such hardware\ntechnologies can play in future supercomputers.\n In this paper we explore the porting of the PW advection kernel, an important\ncode component used in a variety of atmospheric simulations and accounting for\naround 40 % of the runtime of the popular Met Office NERC Cloud model (MONC).\nBuilding upon previous work which ported this kernel to an older generation of\nXilinx FPGA, we target latest generation Xilinx Alveo U280 and Intel Stratix 10\nFPGAs. Exploring the development of a dataflow design which is performance\nportable between vendors, we then describe implementation differences between\nthe tool chains and compare kernel performance between FPGA hardware. This is\nfollowed by a more general performance comparison, scaling up the number of\nkernels on the Xilinx Alveo and Intel Stratix 10, against a 24 core Xeon\nPlatinum Cascade Lake CPU and NVIDIA Tesla V100 GPU. When overlapping the\ntransfer of data to and from the boards with compute, the FPGA solutions\nconsiderably outperform the CPU and, whilst falling short of the GPU in terms\nof performance, demonstrate power usage benefits, with the Alveo being\nespecially power efficient. The result of this work is a comparison and set of\ndesign techniques that apply both to this specific atmospheric advection kernel\non Xilinx and Intel FPGAs, and that are also of interest more widely when\nlooking to accelerate HPC codes on a variety of reconfigurable architectures.\n