2024/06/26 by Bucheli, Florian, Castañeda, Oscar, Marti, Gian +1
#FOS: Computer and information sciences #FOS: Electrical engineering #Hardware Architecture (cs.AR) #Signal Processing (eess.SP) #electronic engineering #information engineering
paper · doi:10.48550/arxiv.2406.18149
We present the first multi-user (MU) multiple-input multiple-output (MIMO) receiver ASIC that mitigates jamming attacks. The ASIC implements a recent nonlinear algorithm that performs joint jammer mitigation (via spatial filtering) and data detection (using a box prior on the data symbols). Our design supports 8 user equipments (UEs) and 32 basestation (BS) antennas, QPSK and 16-QAM with soft-outputs, and enables the mitigation of single-antenna barrage jammers and smart jammers. The fabricated 22 nm FD-SOI ASIC includes preprocessing, has a core area of 3.78 mm2, achieves a throughput of 267 Mb/s while consuming 583 mW, and is the only existing design that enables reliable data detection under jamming attacks.