A Jammer-Resilient 2.87 mm² 1.28 MS/s 310 mW Multi-Antenna Synchronization ASIC in 65 nm

2025/11/26 by Flurin Arquint, Oscar Castañeda, Arquint, Flurin +5
Computer Science · #Cryptographic Implementations and Security #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Network Time Synchronization Technologies #Security in Wireless Sensor Networks

paper · pdf · doi:10.48550/arxiv.2511.21451

openalex publication_date 2025/11/26 · openalex created_date 2025/11/28 · openalex updated_date 2026/07/28

Abstract

We present the first ASIC implementation of jammer-resilient multi-antenna time synchronization. The ASIC implements a recent algorithm that mitigates jamming attacks on synchronization signals using multi-antenna processing. Our design supports synchronization between a single-antenna transmitter and a 16-antenna receiver while mitigating smart jammers with up to two transmit antennas. The fabricated 65 nm ASIC has a core area of 2.87 mm², consumes a power of 310 mW, and supports a sampling rate of 1.28 mega-samples per second (MS/s).

Citations

• Fundamental Limits for Jammer-Resilient Communication in Finite-Resolution MIMO
• Jammer-Resilient Time Synchronization in the MIMO Uplink
• Jamming-Resistant Receivers for the Massive MIMO Uplink

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