2022/01/26 by Alves de Barros-Naviner, Lirida, Naviner, Jean-François, Teixeira Franco, Denis +1
#Reliability #combinational logic #fault tolerance
paper · doi:10.4230/dagsemproc.08371.5
This paper deals with digital VLSI design aspects related to reliability. The focus is on the problem of reliability evaluation in combinational logic circuits.We present some methods for this evaluation that can be easily integrated in a tradidional design flow. Also we describe suitable metrics for performance estimation of concurrent error detection schemes.