2023/01/17 by Michael J. Degerstrom, Degerstrom, Michael J., Chad M. Smutzer +7
Engineering · #Advancements in PLL and VCO Technologies #Electromagnetic Compatibility and Noise Suppression #FOS: Computer and information sciences #FOS: Electrical engineering #Networking and Internet Architecture (cs.NI) #Semiconductor Lasers and Optical Devices #Signal Processing (eess.SP) #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.2304.01913
openalex publication_date 2023/01/17 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
An earlier study of a high layer-count test board using plated-through-hole (PTH) vias and a limited quantity of laser vias was shown to be capable of supporting 112 Gb/s PAM-4 links (or equivalent signaling having 28 GHz (Nyquist) bandwidth). This original board design was then rebuilt using a different fabricator, and the test results revealed a significant decrease in the bandwidth of the vias. These results led to the development of a set of design specifications that PCB vendors can easily validate, which will ensure that the use of high layer-count boards with PTH technology are viable for emerging 112 Gb/s PAM-4 links.