2023/01/17 by Michael J. Degerstrom, Degerstrom, Michael J., Chad M. Smutzer +5
Engineering · #3D IC and TSV technologies #Electromagnetic Compatibility and Noise Suppression #Electrostatic Discharge in Electronics #FOS: Computer and information sciences #FOS: Electrical engineering #Networking and Internet Architecture (cs.NI) #Signal Processing (eess.SP) #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.2304.01909
openalex publication_date 2023/01/17 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Although next generation (>28 Gbps) SerDes standards have been contemplated for several years, it has not been clear whether PCB structures supporting 56 Gbps NRZ will be feasible and practical. In this paper, we assess a number of specific PCB design strategies (related to pin-field breakouts, via stubs, and fiber weave skew) both through simulation and through measurement of a wide range of structures on a PCB test vehicle. We demonstrate that conventional approaches in many cases will not be sufficient, but that modest (manufacturable) design changes can enable low-skew 56 Gbps NRZ channels having acceptable insertion and return loss.