Efficient Hardware Implementation of Incremental Learning and Inference on Chip

2019/11/17 by Ghouthi Boukli Hacene, Vincent Gripon, Hacene, Ghouthi Boukli +7
Computer Science · #Advanced Data Compression Techniques #Computer Vision and Pattern Recognition (cs.CV) #Domain Adaptation and Few-Shot Learning #FOS: Computer and information sciences #Face and Expression Recognition #Machine Learning and ELM

paper · pdf · doi:10.48550/arxiv.1911.07847

openalex publication_date 2019/11/18 · openalex created_date 2020/09/08 · openalex updated_date 2026/07/28

Abstract

In this paper, we tackle the problem of incrementally learning a classifier, one example at a time, directly on chip. To this end, we propose an efficient hardware implementation of a recently introduced incremental learning procedure that achieves state-of-the-art performance by combining transfer learning with majority votes and quantization techniques. The proposed design is able to accommodate for both new examples and new classes directly on the chip. We detail the hardware implementation of the method (implemented on FPGA target) and show it requires limited resources while providing a significant acceleration compared to using a CPU.

Citations

• Compressing Deep Convolutional Networks using Vector Quantization
• A Survey on Transfer Learning
• Shift: A Zero FLOP, Zero Parameter Alternative to Spatial Convolutions
• Learning to Prune Filters in Convolutional Neural Networks
• Constructing Fast Network through Deconstruction of Convolution

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