FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training

2022/12/07 by Liu, Keren, Börjeson, Erik, Häger, Christian +1
#FOS: Computer and information sciences #FOS: Electrical engineering #Information Theory (cs.IT) #Machine Learning (cs.LG) #Machine Learning (stat.ML) #Signal Processing (eess.SP) #electronic engineering #information engineering

paper · doi:10.48550/arxiv.2212.03515

Abstract

We design and implement an adaptive machine learning equalizer that alternates multiple linear and nonlinear computational layers on an FPGA. On-chip training via gradient backpropagation is shown to allow for real-time adaptation to time-varying channel impairments.

Related

• Achieving High Throughput with a Trainable Neural-Network-Based Equalizer for Communications on FPGA
• Long Short-Term Memory Neuron Equalizer
• A survey on FPGA-based accelerator for ML models
• Enabling Incremental Training with Forward Pass for Edge Devices
• An FPGA Accelerated Method for Training Feed-forward Neural Networks Using Alternating Direction Method of Multipliers and LSMR