2021/03/05 by Riccardo Paccagnella, Licheng Luo, Paccagnella, Riccardo +3 · 2 voices · 1 citation
Computer Science · #Channel (broadcasting) #Computer architecture #Computer network #Computer science #Computer security #Cryptographic Implementations and Security #Cryptography #Embedded system #Exploit #Granularity #Interconnection #Leverage (statistics) #Multi-core processor #Operating system #Parallel computing #Physical Unclonable Functions (PUFs) and Hardware Security #Security and Verification in Computing #Side channel attack #cs.AR #cs.CR
paper · pdf · doi:10.48550/arxiv.2103.03443
This is the extended version of a paper that appears in USENIX Security 2021
arxiv created 2021/03/05 · openalex publication_date 2021/03/05 · arxiv updated 2021/03/08 · openalex created_date 2021/03/15 · openalex updated_date 2026/07/28
We introduce the first microarchitectural side channel attacks that leverage contention on the CPU ring interconnect. There are two challenges that make it uniquely difficult to exploit this channel. First, little is known about the ring interconnect's functioning and architecture. Second, information that can be learned by an attacker through ring contention is noisy by nature and has coarse spatial granularity. To address the first challenge, we perform a thorough reverse engineering of the sophisticated protocols that handle communication on the ring interconnect. With this knowledge, we build a cross-core covert channel over the ring interconnect with a capacity of over 4 Mbps from a single thread, the largest to date for a cross-core channel not relying on shared memory. To address the second challenge, we leverage the fine-grained temporal patterns of ring contention to infer a victim program's secrets. We demonstrate our attack by extracting key bits from vulnerable EdDSA and RSA implementations, as well as inferring the precise timing of keystrokes typed by a victim user.