2023/06/24 by Madhava Sarma Vemuri, Vemuri, Madhava Sarma, Umamaheswara Rao Tida +1
Computer Science · Engineering · #3D IC and TSV technologies #Emerging Technologies (cs.ET) #FOS: Computer and information sciences #FOS: Electrical engineering #Interconnection Networks and Systems #Semiconductor materials and devices #Systems and Control (eess.SY) #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.2306.14033
openalex publication_date 2023/06/24 · openalex created_date 2023/06/28 · openalex updated_date 2026/07/28
Monolithic 3D integration has become a promising solution for future computing needs. The metal inter-layer via (MIV) forms interconnects between substrate layers in Monolithic 3D integration. Despite small size of MIV, the area overhead can become a major limitation for efficient M3D integration and, thus needs to be addressed. Previous works focused on the utilization of the substrate area around MIV to reduce this area overhead significantly but suffers from increased leakage and scaling factors. In this work, we discuss MIV-transistor realization that addresses both leakage and scaling issue along with similar area overhead reduction compared with previous works and, thus can be utilized efficiently. Our simulation results suggest that the leakage current (ID,leak) has reduced by 14K× and, the maximum current (ID,max) increased by 58% for the proposed MIV-transistor compared with the previous implementation. In addition, performance metrics of the inverter realization with our proposed MIV-transistor specifically the delay, slew time and power consumption reduced by 11.6%, 17.9% and, 4.5% respectively compared with the previous implementation with same MIV area overhead reduction.