2015/03/12 by François Leduc-Primeau, Leduc-Primeau, François, Frank R. Kschischang +3
Computer Science · Engineering · #Advanced Wireless Communication Techniques #Error Correcting Code Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Information Theory (cs.IT) #Quantum Computing Algorithms and Architecture
paper · pdf · doi:10.48550/arxiv.1503.03880
openalex publication_date 2015/03/12 · openalex created_date 2022/10/05 · openalex updated_date 2026/07/28
This paper proposes a "quasi-synchronous" design approach for signal\nprocessing circuits, in which timing violations are permitted, but without the\nneed for a hardware compensation mechanism. The case of a low-density\nparity-check (LDPC) decoder is studied, and a method for accurately modeling\nthe effect of timing violations at a high level of abstraction is presented.\nThe error-correction performance of code ensembles is then evaluated using\ndensity evolution while taking into account the effect of timing faults.\nFollowing this, several quasi-synchronous LDPC decoder circuits based on the\noffset min-sum algorithm are optimized, providing a 23%-40% reduction in energy\nconsumption or energy-delay product, while achieving the same performance and\noccupying the same area as conventional synchronous circuits.\n