Memory Efficient Decoders using Spatially Coupled Quasi-Cyclic LDPC Codes

2013/05/24 by Vikram Arkalgud Chandrasetty, Chandrasetty, Vikram Arkalgud, Sarah J. Johnson +3
Computer Science · Engineering · Mathematics · #Advanced Wireless Communication Techniques #Error Correcting Code Techniques #Telecommunications and Broadcasting Technologies #cs.IT #math.IT

paper · pdf · doi:10.48550/arxiv.1305.5625

6 pages, 8 figures, 1 table, submitted to journal

arxiv created 2013/10/17 · arxiv updated 2013/10/18

Abstract

In this paper we propose the construction of Spatially Coupled Low-Density Parity-Check (SC-LDPC) codes using a periodic time-variant Quasi-Cyclic (QC) algorithm. The QC based approach is optimized to obtain memory efficiency in storing the parity-check matrix in the decoders. A hardware model of the parity-check storage units has been designed for Xilinx FPGA to compare the logic and memory requirements for various approaches. It is shown that the proposed QC SC-LDPC code (with optimization) can be stored with reasonable logic resources and without the need of block memory in the FPGA. In addition, a significant improvement in the processing speed is also achieved.

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