Intelligent Bees for QoS Routing in Networks-on-Chip

2011/09/04 by Peibo Xie, Xie, Peibo, Huaxi Gu +1
Computer Science · #Embedded Systems Design Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Interconnection Networks and Systems #Software-Defined Networks and 5G #cs.AR

paper · pdf · doi:10.48550/arxiv.1109.0755

4 pages, 4 figures, IEEE 2010 Second Pacific-Asia Conference on Circuits, Communications and System (PACCS)

arxiv created 2011/09/04 · openalex publication_date 2011/09/04 · arxiv updated 2011/09/06 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

Networks-on-Chip (NoCs) for future many-core processor platforms integrate more and more heterogeneous components of different types and many real-time and latency-sensitive applications can run on a single chip concurrently. The reconfigurable FPGA and reconfigurable NoCs have emerged for the purpose of reusability. Those types' traffics within NoCs exhibit diverse, burst, and unpredictable communication patterns. QoS guaranteed mechanisms are necessary to provide guaranteed throughput (GT) or guaranteed bandwidth (GB) performance for NoCs. In this paper, we propose a QoS routing algorithm inspired by bees' foraging behaviors to provide guaranteed bandwidth performance. Virtual circuits and Spatial Division Multiplexing are employed to maintain available paths for different type's traffics.

Related

• Algorithms for Network-on-Chip Design with Guaranteed QoS
• A Practical Approach for Circuit Routing on Dynamic Reconfigurable\n Devices
• Performance Enhancement of Routers in Networks-on-Chip Using Dynamic Virtual Channels Allocation
• A General, Fault tolerant, Adaptive, Deadlock-free Routing Protocol for Network-on-chip
• Network-on-Chip with load balancing based on interleave of flits\n technique