2016/07/27 by Navid Khoshavi, Khoshavi, Navid, Xunchao Chen +5
Computer Science · Engineering · #Advanced Data Storage Technologies #Caching and Content Delivery #Emerging Technologies (cs.ET) #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Low-power high-performance VLSI design #Parallel Computing and Optimization Techniques
paper · pdf · doi:10.48550/arxiv.1607.08086
openalex publication_date 2016/07/27 · openalex created_date 2022/10/02 · openalex updated_date 2026/07/28
As capacity and complexity of on-chip cache memory hierarchy increases, the\nservice cost to the critical loads from Last Level Cache (LLC), which are\nfrequently repeated, has become a major concern. The processor may stall for a\nconsiderable interval while waiting to access the data stored in the cache\nblocks in LLC, if there are no independent instructions to execute. To provide\naccelerated service to the critical loads requests from LLC, this work\nconcentrates on leveraging the additional capacity offered by replacing\nSRAM-based L2 with Spin-Transfer Torque Random Access Memory (STT-RAM) to\naccommodate frequently accessed cache blocks in exclusive read mode in favor of\nreducing the overall read service time. Our proposed technique partitions L2\ncache into two STT-RAM arrangements with different write performance and data\nretention time. The retention-relaxed STT-RAM arrays are utilized to\neffectively deal with the regular L2 cache requests while the high retention\nSTT-RAM arrays in L2 are selected for maintaining repeatedly read accessed\ncache blocks from LLC by incurring negligible energy consumption for data\nretention. Our experimental results show that the proposed technique can reduce\nthe mean L2 read miss ratio by 51.4% and increase the IPC by 11.7% on average\nacross PARSEC benchmark suite while significantly decreasing the total L2\nenergy consumption compared to conventional SRAM-based L2 design.\n