Marco Zanuso

1. A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-\rm fs_{\rm rms} Integrated Jitter at 4.5-mW Power
   2011/09/01 by Davide Tasca, Marco Zanuso, Giovanni Marzin +3 · 23 citations
   Engineering · #Advancements in PLL and VCO Technologies #Analog and Mixed-Signal Circuit Design #CMOS #Direct digital synthesizer #Electrical engineering #Electronic engineering #Engineering #Frequency synthesizer #Jitter #Optics #Optoelectronics #Oversampling #PLL multibit #Phase noise #Phase-locked loop #Photonic and Optical Devices #Physics #dBc