Tang, Jinwei

1. HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design
   2024/12/06 by Tang, Jinwei, Qin, Jiayin, Thorat, Kiran +5 · 3 citations
   #Artificial Intelligence (cs.AI) #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Machine Learning (cs.LG)