Zeshan Chishti
- Improving DRAM Performance by Parallelizing Refreshes with Accesses
2017/12/21 by Kevin K. Chang, Donghyuk Lee, Zeshan Chishti +4 · 3 citations
Computer Science · #cs.AR
- TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems
2019/07/03 by Vinson Young, Zeshan Chishti, Young, Vinson +3 · 1 citation
Computer Science · Engineering · #Advanced Data Storage Technologies #Advanced Memory and Neural Computing #Bandwidth (computing) #CAS latency #Cache #Computer hardware #Computer network #Computer science #Dram #Embedded system #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Instruction prefetch #Latency (audio) #Memory bandwidth #Memory controller #Metadata #Operating system #Parallel Computing and Optimization Techniques #Parallel computing #Semiconductor memory #Telecommunications #cs.AR
- Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses
2016/01/24 by Kevin Kai-Wei Chang, Chang, Kevin Kai-Wei, Donghyuk Lee +11 · 1 citation
Computer Science · #Advanced Data Storage Technologies #Cloud Computing and Resource Management #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Parallel Computing and Optimization Techniques #cs.AR
- Reducing cache power with low-cost, multi-bit error-correcting codes
2010/06/19 by Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti +3 · 1 citation
Computer Science · Engineering · #Low-power high-performance VLSI design #Parallel Computing and Optimization Techniques #Radiation Effects in Electronics