2007/11/13 by Volodymyr Kindratenko, Volodymyr V. Kindratenko, Robert J. Brunner +4 · 1 voice · 1 citation
Computer Science · Physics and Astronomy · #Astrophysics (astro-ph) #Embedded Systems Design Techniques #FOS: Physical sciences #Interconnection Networks and Systems #Parallel Computing and Optimization Techniques #astro-ph
paper · pdf · doi:10.48550/arxiv.0711.2034
On speeding up 2PCF calculations using field-programmable gate arrays, appeared in Proc. 3rd Annual Reconfigurable Systems Summer Institute - RSSI'07, 2007, 8 pages
arxiv created 2007/11/13 · openalex publication_date 2007/11/13 · arxiv published 2007/11/13 · arxiv updated 2007/11/13 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
In this case study, we investigate the impact of workload balance on the performance of multi-FPGA codes. We start with an application in which two distinct kernels run in parallel on two SRC-6 MAP processors. We observe that one of the MAP processors is idle 18% of the time while the other processor is fully utilized. We investigate a task redistribution schema which serializes the execution of the two kernels, yet parallelizes execution of each individual kernel by spreading the workload between two MAP processors. This implementation results in a near 100% utilization of both MAP processors and the overall application performance is improved by 9%.