Partial Reversible Gates(PRG) for Reversible BCD Arithmetic

2007/11/16 by Himanshu Thapliyal, Thapliyal, Himanshu, Hamid R. Arabnia +5
Computer Science · #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Numerical Methods and Algorithms #Quantum Computing Algorithms and Architecture #Quantum-Dot Cellular Automata

paper · pdf · doi:10.48550/arxiv.0711.2674

openalex publication_date 2007/11/16 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Furthermore, in the recent years reversible logic has emerged as a promising computing paradigm having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The major goal in reversible logic is to minimize the number of reversible gates and garbage outputs. Thus, this paper proposes the novel concept of partial reversible gates that will satisfy the reversibility criteria for specific cases in BCD arithmetic. The partial reversible gate is proposed to minimize the number of reversible gates and garbage outputs, while designing the reversible BCD arithmetic circuits.

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