Efficient Precision-Scalable Hardware for Microscaling (MX) Processing in Robotics Learning

2025/05/28 by Stef Cuyckens, Xiaoling Yi, Cuyckens, Stef +7 · 3 citations
Computer Science · Engineering · #Advanced Neural Network Applications #FOS: Computer and information sciences #Ferroelectric and Negative Capacitance Devices #Hardware Architecture (cs.AR) #Parallel Computing and Optimization Techniques #Robotics (cs.RO)

paper · doi:10.48550/arxiv.2505.22404

openalex publication_date 2025/05/28 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/30

Abstract

Autonomous robots require efficient on-device learning to adapt to new environments without cloud dependency. For this edge training, Microscaling (MX) data types offer a promising solution by combining integer and floating-point representations with shared exponents, reducing energy consumption while maintaining accuracy. However, the state-of-the-art continuous learning processor, namely Dacapo, faces limitations with its MXINT-only support and inefficient vector-based grouping during backpropagation. In this paper, we present, to the best of our knowledge, the first work that addresses these limitations with two key innovations: (1) a precision-scalable arithmetic unit that supports all six MX data types by exploiting sub-word parallelism and unified integer and floating-point processing; and (2) support for square shared exponent groups to enable efficient weight handling during backpropagation, removing storage redundancy and quantization overhead. We evaluate our design against Dacapo under iso-peak-throughput on four robotics workloads in TSMC 16nm FinFET technology at 400MHz, reaching a 51% lower memory footprint, and 4x higher effective training throughput, while achieving comparable energy efficiency, enabling efficient robotics continual learning at the edge.

Citations

• Oscillation-Reduced MXFP4 Training for Vision Transformers
• Training LLMs with MXFP4
• FlexiBit: Fully Flexible Precision Bit-parallel Accelerator Architecture for Arbitrary Mixed Precision AI
• Exploring FPGA designs for MX and beyond
• Post Training Quantization of Large Language Models with Microscaling Formats
• QServe: W4A8KV4 Quantization and System Co-design for Efficient LLM Serving
• Microscaling Data Formats for Deep Learning
• Edge-Assisted On-Device Model Update for Video Analytics in Adverse Environments
• Precision-aware Latency and Energy Balancing on Multi-Accelerator Platforms for DNN Inference
• With Shared Microexponents, A Little Shifting Goes a Long Way
• FlexBlock: A Flexible DNN Training Accelerator with Multi-Mode Block Floating Point Support
• Edge Robotics: Edge-Computing-Accelerated Multi-Robot Simultaneous Localization and Mapping
• FAST: DNN Training Under Variable Precision Block Floating Point with Stochastic Rounding
• Continual World: A Robotic Benchmark For Continual Reinforcement\n Learning
• Ekya: Continuous Learning of Video Analytics Models on Edge Compute\n Servers
• Deep Reinforcement Learning in a Handful of Trials using Probabilistic Dynamics Models

Cited by

• Tensor-Compressed and Fully-Quantized Training of Neural PDE Solvers
• Ten-Four: An Open-Source Fused Dot Product Unit for Mixed-Precision GPGPU Tensor Cores
• Precision-Scalable Microscaling Datapaths with Optimized Reduction Tree for Efficient NPU Integration

Related

• Precision-Scalable Microscaling Datapaths with Optimized Reduction Tree for Efficient NPU Integration
• Tiny Robot Learning: Challenges and Directions for Machine Learning in Resource-Constrained Robots
• Microscaling Data Formats for Deep Learning
• MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products
• Tin-Tin: Towards Tiny Learning on Tiny Devices with Integer-based Neural Network Training