2025/03/28 by Owen Medeiros, Medeiros, Owen, Matteo Castellani +15 · 2 citations
Engineering · Physics and Astronomy · #Advancements in Semiconductor Devices and Circuit Design #Applied Physics (physics.app-ph) #FOS: Physical sciences #Nanowire Synthesis and Applications #Quantum and electron transport phenomena
paper · pdf · doi:10.48550/arxiv.2503.22897
openalex publication_date 2025/03/28 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Developing ultra-low-energy superconducting computing and fault-tolerant quantum computing will require scalable superconducting memory. While conventional superconducting logic-based memory cells have facilitated early demonstrations, their large footprint poses a significant barrier to scaling. Nanowire-based superconducting memory cells offer a compact alternative, but high error rates have hindered their integration into large arrays. In this work, we present a superconducting nanowire memory array designed for scalable row-column operation, achieving a functional density of 2.6 Mb/cm2. The array operates at 1.3 K, where we implement and characterize multi-flux quanta state storage and destructive readout. By optimizing write and read pulse sequences, we minimize bit errors while maximizing operational margins in a 4× 4 array. Circuit-level simulations further elucidate the memory cell's dynamics, providing insight into performance limits and stability under varying pulse amplitudes. We experimentally demonstrate stable memory operation with a minimum bit error rate of 10-5. These results suggest a promising path for scaling superconducting nanowire memories to high-density architectures, offering a foundation for energy-efficient memory in superconducting electronics.