ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model

2025/04/20 by Qin, Haiyan, Xie, Zhiwei, Li, Jingjing +4 · 10 citations
#Artificial Intelligence (cs.AI) #FOS: Computer and information sciences #Hardware Architecture (cs.AR)

paper · doi:10.48550/arxiv.2504.14560

Abstract

Large Language Models (LLMs) have advanced Verilog code generation significantly, yet face challenges in data quality, reasoning capabilities, and computational efficiency. This paper presents ReasoningV, a novel model employing a hybrid reasoning strategy that integrates trained intrinsic capabilities with dynamic inference adaptation for Verilog code generation. Our framework introduces three complementary innovations: (1) ReasoningV-5K, a high-quality dataset of 5,000 functionally verified instances with reasoning paths created through multi-dimensional filtering of PyraNet samples; (2) a two-stage training approach combining parameter-efficient fine-tuning for foundational knowledge with full-parameter optimization for enhanced reasoning; and (3) an adaptive reasoning mechanism that dynamically adjusts reasoning depth based on problem complexity, reducing token consumption by up to 75% while preserving performance. Experimental results demonstrate ReasoningV's effectiveness with a pass@1 accuracy of 57.8% on VerilogEval-human, achieving performance competitive with leading commercial models like Gemini-2.0-flash (59.5%) and exceeding the previous best open-source model by 10.4 percentage points. ReasoningV offers a more reliable and accessible pathway for advancing AI-driven hardware design automation, with our model, data, and code available at https://github.com/BUAA-CLab/ReasoningV.

Cited by

• CircuitWeave: Topology-Behavior Alignment for Executable Multimodal RTL Generation
• Benchmarking LLMs for Verilog Design Flows
• QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Design
• VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generation
• Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
• REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Models
• DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base
• VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
• Understanding and Mitigating Errors of LLM-Generated RTL Code
• ChipSeek-R1: Generating Human-Surpassing RTL with LLM via Hierarchical Reward-Driven Reinforcement Learning

Related

• QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation
• VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification
• VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning
• VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation
• VeriGen: A Large Language Model for Verilog Code Generation