2024/11/20 by Naoya Hatta, Hatta, Naoya, Taichi Ishitani +3
Computer Science · Engineering · #B.6.3 #Embedded Systems Design Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Parallel Computing and Optimization Techniques #Real-time simulation and control systems
paper · pdf · doi:10.48550/arxiv.2411.12983
openalex publication_date 2024/11/20 · openalex created_date 2024/11/24 · openalex updated_date 2026/07/28
Veryl, a hardware description language based on SystemVerilog, offers optimized syntax tailored for logic design, ensuring synthesizability and simplifying common constructs. It prioritizes interoperability with SystemVerilog, allowing for smooth integration with existing projects while maintaining high readability. Additionally, Veryl includes a comprehensive set of development support tools, such as package managers and real-time checkers, to boost productivity and streamline the design process. These features empower designers to conduct high-quality hardware design efficiently.