2009/01/01 by Rolf Drechsler, Stephan Eggersglüß, Drechsler, Rolf +5
Computer Science · Engineering · #ATPG #Boolean Satisfiability #Circuit #Integrated Circuits and Semiconductor Failure Analysis #SAT #VLSI and Analog Circuit Testing #VLSI and FPGA Design Techniques
paper · doi:10.4230/dagsemproc.08351.6
openalex publication_date 2009/01/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for Automatic Test Pattern Generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on Conjunctive Normal Forms (CNF), the problem has to be transformed. During transformation, relevant information about the problem might get lost and therefore is not available in the solving process. In the following we briefly motivate the problem and provide the latest developments in the field. The technique was implemented and experimental results are presented. The approach was combined with the ATPG framework of NXP Semiconductors. Significant improvements in overall performance and robustness are demonstrated.