2022/11/30 by Jackson Melchert, Melchert, Jackson, Keyi Zhang +9 · 1 citation
Computer Science · Engineering · #3D IC and TSV technologies #Compiler #Computer architecture #Computer science #Design space exploration #Embedded Systems Design Techniques #Embedded system #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Interconnection #Operating system #Parallel computing #Python (programming language) #Routing (electronic design automation) #VLSI and FPGA Design Techniques
paper · pdf · doi:10.48550/arxiv.2211.17207
openalex publication_date 2022/11/30 · openalex created_date 2025/10/10 · openalex updated_date 2026/08/05
The architecture of a coarse-grained reconfigurable array (CGRA) interconnect has a significant effect on not only the flexibility of the resulting accelerator, but also its power, performance, and area. Design decisions that have complex trade-offs need to be explored to maintain efficiency and performance across a variety of evolving applications. This paper presents Canal, a Python-embedded domain-specific language (eDSL) and compiler for specifying and generating reconfigurable interconnects for CGRAs. Canal uses a graph-based intermediate representation (IR) that allows for easy hardware generation and tight integration with place and route tools. We evaluate Canal by constructing both a fully static interconnect and a hybrid interconnect with ready-valid signaling, and by conducting design space exploration of the interconnect architecture by modifying the switch box topology, the number of routing tracks, and the interconnect tile connections. Through the use of a graph-based IR for CGRA interconnects, the eDSL, and the interconnect generation system, Canal enables fast design space exploration and creation of CGRA interconnects.