2005/08/04 by John Robert Burger, Burger, John Robert · 1 citation
Computer Science · #B.7.1 #C.1.2 #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Quantum Computing Algorithms and Architecture #Quantum Information and Cryptography #Quantum-Dot Cellular Automata #cs.AR
paper · pdf · doi:10.48550/arxiv.cs/0508038
arxiv created 2005/08/04 · openalex publication_date 2005/08/04 · arxiv updated 2009/12/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Wiring diagrams are given for a quantum algorithm processor in CMOS to compute, in parallel, all divisors of an n-bit integer. Lines required in a wiring diagram are proportional to n. Execution time is proportional to the square of n.