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A Variable Node Design with Check Node Aware Quantization Leveraging 2-Bit LDPC Decoding

2022/11/13 by Philipp Mohr, Mohr, Philipp, Gerhard Bauch +1
Computer Science · Engineering · #Advanced Data Compression Techniques #Advanced Wireless Communication Techniques #Error Correcting Code Techniques #FOS: Computer and information sciences #Information Theory (cs.IT)

paper · pdf · doi:10.48550/arxiv.2211.06973

openalex publication_date 2022/11/13 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

For improving coarsely quantized decoding of LDPC codes, we propose a check node aware design of the variable node update. In contrast to previous works, we optimize the variable node to explicitly maximize the mutual information preserved in the check-to-variable instead of the variable-to-check node messages. The extended optimization leads to a significantly different solution for the compression operation at the variable node. Simulation results for regular LDPC codes confirm that the check node aware design, especially for very coarse quantization with 2- or 3-bit messages, achieves performance gains of up to 0.2 dB - without additional hardware costs. We also show that the 2-bit message resolution enables a very efficient implementation of the check node update, which requires only 2/9 of the 3-bit check node's transistor count and reduces the signal propagation delay by a factor of 4.

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