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Stack up your chips: Betting on 3D integration to augment Moore's Law scaling

2020/05/21 by Saurabh Sinha, Sinha, Saurabh, Xiaoqing Xu +9
Computer Science · Engineering · #Embedded Systems Design Techniques #FOS: Computer and information sciences #FOS: Electrical engineering #Hardware Architecture (cs.AR) #Parallel Computing and Optimization Techniques #Systems and Control (eess.SY) #VLSI and FPGA Design Techniques #electronic engineering #information engineering

paper · pdf · doi:10.48550/arxiv.2005.10866

openalex publication_date 2020/05/21 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

3D integration, i.e., stacking of integrated circuit layers using parallel or sequential processing is gaining rapid industry adoption with the slowdown of Moore's law scaling. 3D stacking promises potential gains in performance, power and cost but the actual magnitude of gains varies depending on end-application, technology choices and design. In this talk, we will discuss some key challenges associated with 3D design and how design-for-3D will require us to break traditional silos of micro-architecture, circuit/physical design and manufacturing technology to work across abstractions to enable the gains promised by 3D technologies.

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