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1/f Noise Reduction using In-Pixel Chopping in CMOS Image Sensor

2018/07/27 by Kapil Jainwal, Jainwal, Kapil, Mukul Sarkar +1
Engineering · #Analog and Mixed-Signal Circuit Design #Applied Physics (physics.app-ph) #CCD and CMOS Imaging Sensors #FOS: Physical sciences #Instrumentation and Detectors (physics.ins-det) #Thin-Film Transistor Technologies

paper · pdf · doi:10.48550/arxiv.1807.11577

openalex publication_date 2018/07/27 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

In this paper, an in-pixel chopping technique to reduce the low-frequency or 1/f noise of the source follower (SF) transistor in an active pixel sensor (APS) is presented. The SF low-frequency noise is modulated at higher frequencies through chopping, implemented inside the pixel, and in later stage eliminated using low-pass filtering. To implement the chopping, the conventional 3T APS architecture is modified, with only one additional transistor of minimum size per pixel. Reduction in the noise also enhances the dynamic range (DR) of the image sensor. The test circuit is fabricated in UMC 0.18 um standard CMOS technology. The measured results show a reduction of 1/f noise by approximately 22 dB for 50 MHz chopping frequency.

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