Design of CMOS-memristor Circuits for LSTM architecture

2018/06/06 by Kamilya Smagulova, Kazybek Adam, Olga Krestinskaya +1 · 1 voice
#cs.ET

paper · pdf

Abstract

Long Short-Term memory (LSTM) architecture is a well-known approach for building recurrent neural networks (RNN) useful in sequential processing of data in application to natural language processing. The near-sensor hardware implementation of LSTM is challenged due to large parallelism and complexity. We propose a 0.18 m CMOS, GST memristor LSTM hardware architecture for near-sensor processing. The proposed system is validated in a forecasting problem based on Keras model.

Discussions

• Design of CMOS-memristor Circuits for LSTM architecture [hn, 58 points, 15 comments]

Related

• Memristive LSTM network hardware architecture for time-series predictive\n modeling problem
• LiteLSTM Architecture Based on Weights Sharing for Recurrent Neural Networks
• LiteLSTM Architecture for Deep Recurrent Neural Networks
• SpRRAM: A Predefined Sparsity Based Memristive Neuromorphic Circuit for Low Power Application
• Current Opinions on Memristor-Accelerated Machine Learning Hardware