2020/09/02 by Debjyoti Bhattacharjee, Bhattacharjee, Debjyoti, Anupam Chattopadhyay +7
Computer Science · Engineering · #Advanced Memory and Neural Computing #CCD and CMOS Imaging Sensors #Emerging Technologies (cs.ET) #FOS: Computer and information sciences #Ferroelectric and Negative Capacitance Devices #Hardware Architecture (cs.AR) #cs.AR #cs.ET
paper · pdf · doi:10.48550/arxiv.2009.00881
9 pages
arxiv created 2020/09/02 · openalex publication_date 2020/09/02 · arxiv updated 2020/09/03 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Data-intensive applications are poised to benefit directly from processing-in-memory platforms, such as memristive Memory Processing Units, which allow leveraging data locality and performing stateful logic operations. Developing design automation flows for such platforms is a challenging and highly relevant research problem. In this work, we investigate the problem of minimizing delay under arbitrary area constraint for MAGIC-based in-memory computing platforms. We propose an end-to-end area constrained technology mapping framework, CONTRA. CONTRA uses Look-Up Table(LUT) based mapping of the input function on the crossbar array to maximize parallel operations and uses a novel search technique to move data optimally inside the array. CONTRA supports benchmarks in a variety of formats, along with crossbar dimensions as input to generate MAGIC instructions. CONTRA scales for large benchmarks, as demonstrated by our experiments. CONTRA allows mapping benchmarks to smaller crossbar dimensions than achieved by any other technique before, while allowing a wide variety of area-delay trade-offs. CONTRA improves the composite metric of area-delay product by 2.1x to 13.1x compared to seven existing technology mapping approaches.