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IRC: Cross-layer design exploration of Intermittent Robust Computation\n units for IoTs

2019/04/23 by Arman Roohi, Roohi, Arman, Ronald F. DeMara +1
Computer Science · Engineering · #Advanced Memory and Neural Computing #Emerging Technologies (cs.ET) #FOS: Computer and information sciences #Ferroelectric and Negative Capacitance Devices #Hardware Architecture (cs.AR) #Quantum Computing Algorithms and Architecture

paper · pdf · doi:10.48550/arxiv.1904.10564

openalex publication_date 2019/04/23 · openalex created_date 2022/07/24 · openalex updated_date 2026/07/28

Abstract

Energy-harvesting-powered computing offers intriguing and vast opportunities\nto dramatically transform the landscape of the Internet of Things (IoT) devices\nby utilizing ambient sources of energy to achieve battery-free computing. In\norder to operate within the restricted energy capacity and intermittency\nprofile, it is proposed to innovate Intermittent Robust Computation (IRC) Unit\nas a new duty-cycle-variable computing approach leveraging the non-volatility\ninherent in spin-based switching devices. The foundations of IRC will be\nadvanced from the device-level upwards, by extending a Spin Hall Effect\nMagnetic Tunnel Junction (SHE-MTJ) device. The device will then be used to\nrealize SHE-MTJ Majority/Polymorphic Gate (MG/PG) logic approaches and\nlibraries. Then a Logic-Embedded Flip-Flop (LE-FF) is developed to realize\nrudimentary Boolean logic functions along with an inherent state-holding\ncapability within a compact footprint. Finally, the NV-Clustering synthesis\nprocedure and corresponding tool module are proposed to instantiate the LE-FF\nlibrary cells within conventional Register Transfer Language (RTL)\nspecifications. This selectively clusters together logic and NV state-holding\nfunctionality, based on energy and area minimization criteria. It also realizes\nmiddleware-coherent, intermittent computation without checkpointing,\nmicro-tasking, or software bloat and energy overheads vital to IoT. Simulation\nresults for various benchmark circuits including ISCAS-89 validate\nfunctionality and power dissipation, area, and delay benefits.\n

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