2025/09/24 by Yang, Guang, Zheng, Wei, Chen, Xiang +3 · 1 citation
#Artificial Intelligence (cs.AI) #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Software Engineering (cs.SE)
paper · doi:10.48550/arxiv.2509.20215
LLMs face significant challenges in Verilog generation due to limited domain-specific knowledge. While sampling techniques improve pass@k metrics, hardware engineers need one trustworthy solution rather than uncertain candidates. To bridge this gap, we formulate it as a semantic alignment problem between requirements and Verilog implementations, and propose VCD-RNK, a discriminator model tailored for efficient Verilog code reranking. Specifically, VCD-RNKincorporates Verilog-specific reasoning by distilling expert knowledge across three dimensions: code semantic analysis, test case generation, and functional correctness assessment. By explicitly simulating the above reasoning processes during inference, VCD-RNK effectively avoids computationally intensive test execution in existing methods.