2026/01/15 by Zheng Zhao, Weifeng Zhuang, Yanwu Gu +6
Computer Science · #Quantum Computing Algorithms and Architecture #Parallel Computing and Optimization Techniques #Big Data and Digital Economy
paper · pdf · doi:10.1088/2058-9565/ae6fe6
Abstract Pre-execution calibration is a major bottleneck for operating superconducting quantum processors, and qubit frequency allocation is especially challenging due to crosstalk-coupled objectives. We establish that the widely-used Snake optimizer is mathematically equivalent to block coordinate descent (BCD), providing a rigorous theoretical foundation for this strategy for qubit frequency allocation. Building on this formalization, we present a topology-aware block ordering obtained by casting order selection as a sequence-dependent traveling salesman problem (SD-TSP) and solving it efficiently with a nearest-neighbor heuristic. The SD-TSP cost reflects how a given block choice expands the reduced-circuit footprint required to evaluate the block-local objective, enabling orders that minimize per-epoch evaluation time. Under standard locality-type assumptions, such as local crosstalk or bounded interaction degree, the method achieves linear complexity in qubit count per epoch while maintaining comparable optimization performance. We formalize the calibration objective, clarify when reduced experiments are equivalent or approximate to the full objective, and analyze convergence of the resulting inexact BCD with noisy measurements. Simulations based on a physics-motivated error simulator show that the proposed BCD-nearest neighbor algorithm ordering attains comparable optimization accuracy at markedly lower computational cost than graph-based heuristics (BFS, DFS) and random orders, while also achieving optimization quality comparable to a genetic algorithm baseline. This method is robust to noisy objective-function evaluations and tolerant to moderate nonlocal crosstalk mismatch. These results provide a scalable, implementation-ready workflow for frequency calibration in near-term superconducting processors and, more broadly, for locality-structured calibration tasks in future scalable architectures.