2024/01/01 by Toru Aonishi, Tatsuya Nagasawa, Toshiyuki Koizumi +6 · 8 citations
Computer Science · #Chaos-based Image/Signal Encryption #Computer architecture #Computer science #Embedded system #Field-programmable gate array #Neural Networks and Applications #Parallel computing #Quantum Computing Algorithms and Architecture
paper · pdf · open access · doi:10.1109/access.2024.3504008
published in IEEE Access 12, 175843-175865 (Institute of Electrical and Electronics Engineers)
openalex publication_date 2024/01/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29
To solve large-scale real-world problems, attempts have been made to realize high-speed simulations of quantum Ising machines using field-programmable gate arrays (FPGAs) and to virtually realize networks with a large number of fully coupled spins, which are difficult to achieve in physical systems. We developed an FPGA-implemented cyber coherent Ising machine (cyber CIM) that is much more versatile than previous implementations using FPGAs. Our architecture is versatile because it can be applied to the open-loop CIM, which was proposed when CIM research began, to the closed-loop CIM, which has been used recently, and to the Jacobi successive over-relaxation method. By modifying the sequence control code for the calculation control module, other algorithms such as Simulated Bifurcation (SB) can also be implemented. Earlier studies on large-scale FPGA implementations of SB and CIM used binary or ternary discrete values for connections, whereas cyber CIM used single-precision floating-point format (FP32) values. In addition, cyber CIM uses Zeeman terms that are represented in FP32, which are not present in other large-scale FPGA systems. Our implementation with continuous interaction achievesN=4096on a single FPGA, which is comparable to the single-FPGA implementation of SB with binary interactions withN=4096. Cyber CIM enables applications such as code division multiple access multi-user detector and L0-norm regularization-based compressed sensing which were not possible with earlier FPGA systems, while providing superior calculation speeds, more than ten times faster than the graphic processor unit (GPU) implementation. Increasing parallelism, such as through clustering, can further enhance the calculation speed.