2013/10/21 by Ryuji Kan, Tomohiro Tanaka, Go Sugizaki +12 · 20 citations
Engineering · Computer Science · #Radiation Effects in Electronics #Parallel Computing and Optimization Techniques #Semiconductor materials and devices #Computer science #SerDes #PCI Express #Operating system #Embedded system #Computer hardware #Parallel computing #Field-programmable gate array
paper · doi:10.1109/jssc.2013.2284650
published in IEEE Journal of Solid-State Circuits 49(1), 32-40 (Institute of Electrical and Electronics Engineers)
openalex publication_date 2013/10/21 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29
A 10th generation SPARC64 processor, fabricated in enhanced 28 nm CMOS, runs at 3.0 GHz and contains 16 cores with 24 MB shared L2 cache and system/DDR3/PCIe interfaces in 588 mm2die area. Using H-tree clock distribution network with shield wires, the average clock skew is minimized to 20 ps. Two-step read structure of GPR enables out-of-order execution across register windows. A large SMP system of up to 64 CPUs with ccNUMA uses a newly developed 14.5 GB/s SerDes. Column separation, alternate placement of master and slave latches and well slits are used to mitigate soft errors especially for multi-bit upsets. SER reduction is observed by neutron irradiation experiments.