2024/02/27 by Huiyong Zheng, Zheng, Huiyong, Jiang, Wenning +1
Computer Science · Neuroscience · #Blind Source Separation Techniques #EEG and Brain-Computer Interfaces #FOS: Computer and information sciences #FOS: Electrical engineering #Human-Computer Interaction (cs.HC) #Neuroscience and Neural Engineering #Signal Processing (eess.SP) #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.2402.17538
openalex publication_date 2024/02/27 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
This paper presents the design of a time-division multiplexed capacitively-coupled chopper analog front-end (AFE) with a novel impedance boost loop (IBL) and a novel DC servo loop (DSL). The proposed IBL has two impedance booting loops for compensating leakage current due to parasitic capacitance from the ESD pad and external interconnections, and the chopper. By shifting the compensation node from the feedback pathway to the amplifier's inputs, this work realizes a higher-resolution compensation, boosting the input impedance of the AFE to several tens of GΩ. The proposed DSL consists of a coarse DSL driven by DC supply voltages and a fine DSL driven by five phase-interleaving pulse-width modulated waveforms (PI-PWM). Avoiding the usage of delta-sigma CDAC, the energy efficiency is better than conventional DSLs. Designed in a 0.18-μm CMOS process, the AFE consumes 4.5 μA from a 1.2-V supply. The simulated input referred noise is 0.27 μVrms from 0.5 to 100 Hz in the presence of a 384-mV EDO. With a 10-pF parasitic capacitance, the proposed AFE achieves an input impedance of more than 74.5 GΩ at 1 Hz and 6.4 GΩ at 50 Hz. The simulation results have been robust under 100 Monte-Carlo samples.