2020/01/01 by Zhiyao Xie, Haoxing Ren, Brucek Khailany +4 · 2 citations
Computer Science · Engineering · #Artificial neural network #Constraint (computer-aided design) #Convolutional neural network #Drop (telecommunication) #Low-power high-performance VLSI design #Machine Learning and ELM #Power network design #Speedup #VLSI and Analog Circuit Testing #cs.AR #cs.LG
paper · pdf · doi:10.1109/asp-dac47756.2020.9045574
published as 2020 Asia and South Pacific Design Automation Conference (ASP-DAC 2020)
openalex publication_date 2020/01/01 · openalex created_date 2020/04/03 · arxiv created 2020/11/26 · arxiv updated 2020/11/30 · openalex updated_date 2026/08/05
IR drop is a fundamental constraint required by almost all chip designs. However, its evaluation usually takes a long time that hinders mitigation techniques for fixing its violations. In this work, we develop a fast dynamic IR drop estimation technique, named PowerNet, based on a convolutional neural network (CNN). It can handle both vector-based and vectorless IR analyses. Moreover, the proposed CNN model is general and transferable to different designs. This is in contrast to most existing machine learning (ML) approaches, where a model is applicable only to a specific design. Experimental results show that PowerNet outperforms the latest ML method by 9% in accuracy for the challenging case of vectorless IR drop and achieves a 30× speedup compared to an accurate IR drop commercial tool. Further, a mitigation tool guided by PowerNet reduces IR drop hotspots by 26% and 31% on two industrial designs, respectively, with very limited modification on their power grids.