2018/01/01 by Enzo Rucci, Armando De Giusti, Marcelo Naiouf
Computer Science · #Big Data and Digital Economy #Compiler #Graph Theory and Algorithms #Parallel Computing and Optimization Techniques #Pentium #Thread (computing) #Vectorization (mathematics) #Xeon #Xeon Phi #cs.DC
paper · pdf · doi:10.1007/978-3-319-75214-3_5
Computer Science - CACIC 2017. Springer Communications in Computer and Information Science, vol 790
openalex created_date 2017/12/04 · openalex publication_date 2018/01/01 · arxiv created 2018/11/03 · arxiv updated 2018/11/06 · openalex updated_date 2026/08/05
Manycores are consolidating in HPC community as a way of improving performance while keeping power efficiency. Knights Landing is the recently released second generation of Intel Xeon Phi architecture. While optimizing applications on CPUs, GPUs and first Xeon Phi's has been largely studied in the last years, the new features in Knights Landing processors require the revision of programming and optimization techniques for these devices. In this work, we selected the Floyd-Warshall algorithm as a representative case study of graph and memory-bound applications. Starting from the default serial version, we show how data, thread and compiler level optimizations help the parallel implementation to reach 338 GFLOPS.