1995/12/10 by John Feehrer, Harry F. Jordan · 1 citation
Engineering · #Semiconductor Lasers and Optical Devices #Photonic and Optical Devices #Advanced Optical Network Technologies #Clock gating #Computer science #Clock skew #Synchronous circuit #Electronic circuit #Digital clock manager #Clock drift #Clock signal #Signal edge #Clock network #Clock domain crossing #Clock synchronization #Electronic engineering #Synchronization (alternating current) #Electrical engineering #Computer hardware #Engineering #Channel (broadcasting) #Telecommunications
paper · doi:10.1364/ao.34.008125
openalex publication_date 1995/12/10 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/23
Time-of-flight synchronized optoelectronic circuits capitalize on the highly controllable delays of optical waveguides. Circuits have no latches; synchronization is achieved by adjustment of the lengths of waveguides that connect circuit elements. Clock gating and pulse stretching are used to restore timing and power. A functional circuit requires that every feedback loop contain at least one clock gate to prevent cumulative timing drift and power loss. A designer specifies an ideal circuit, which contains no or very few clock gates. To make the circuit functional, we must identify locations in which to place clock gates. Because clock gates are expensive, add area, and increase delay, a minimal set of locations is desired. We cast this problem in graph-theoretical form as the minimum feedback edge set problem and solve it by using an adaptation of an algorithm proposed in 1966 [IEEE Trans. Circuit Theory CT-13, 399 (1966)]. We discuss a computer-aided-design implementation of the algorithm that reduces computational complexity and demonstrate it on a set of circuits.