1992/09/01 by A. E. Barish, J.P. Eckhardt, M. Mayo +2 · 1 citation
Engineering · #Low-power high-performance VLSI design #Advancements in Semiconductor Devices and Circuit Design #Analog and Mixed-Signal Circuit Design #Emitter-coupled logic #Resistor–transistor logic #IBM #Logic family #Electronic circuit #Logic gate #Modular design #Chip #Pass transistor logic #Electrical engineering #Computer science #Electronic engineering #Computer hardware #Engineering #Logic synthesis #Materials science #Digital electronics #Operating system
paper · doi:10.1147/rd.365.0829
openalex publication_date 1992/09/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/06/26
The performance required for logic gate arrays by the IBM Enterprise System/9000™ (ES/9000™) family of water-cooled processors was obtained by redesigning chips that previously consisted of emitter-coupled logic (ECL) circuits. Multiple bipolar logic circuit families were implemented for the first time on a single IBM chip by using a modular cell approach. In 60% of the ECL circuits, ac coupling in ECL gates reduced the maximum operating power per ECL circuit on ES/9000 chips by 50% and decreased the signal delay per loaded gate by 30%, to 150 ps. About 10–20% of the remaining ECL circuits were replaced by differential current switches (DCS) which dissipated less power and improved the overall chip performance. Circuits to communicate between ECL and DCS circuit families and to improve DCS circuit reliability were included on the ES/9000 chips without affecting logic function density.