2016/07/22 by William S. Song, Vitaliy Gleyzer, Alexei Lomakin +1 · 2 citations
Computer Science · #Clique-width #Directed graph #Exploit #Graph #Graph Theory and Algorithms #Graph partition #Interconnection Networks and Systems #Parallel Computing and Optimization Techniques #Systolic array #Voltage graph #Wait-for graph #cs.AR #cs.DC
paper · pdf · doi:10.1109/hpec.2016.7761635
7 pages, 8 figures, IEEE HPEC 2016
arxiv created 2016/07/22 · openalex created_date 2016/08/23 · openalex publication_date 2016/09/01 · arxiv updated 2016/12/13 · openalex updated_date 2026/08/05
Graph algorithms are increasingly used in applications that exploit large databases. However, conventional processor architectures are inadequate for handling the throughput and memory requirements of graph computation. Lincoln Laboratory's graph-processor architecture represents a rethinking of parallel architectures for graph problems. Our processor utilizes innovations that include a sparse matrix-based graph instruction set, a cacheless memory system, accelerator-based architecture, a systolic sorter, high-bandwidth multidimensional toroidal communication network, and randomized communications. A field-programmable gate array (FPGA) prototype of the new graph processor has been developed with significant performance enhancement over conventional processors in graph computational throughput.