2021/08/31 by Houssam-Eddine Zahaf, Zahaf, Houssam-Eddine, Nicola Capodieci +1
Computer Science · #Distributed #Distributed and Parallel Computing Systems #FOS: Computer and information sciences #FOS: Electrical engineering #Parallel #Parallel Computing and Optimization Techniques #Real-Time Systems Scheduling #Systems and Control (eess.SY) #and Cluster Computing (cs.DC) #electronic engineering #information engineering
paper · doi:10.48550/arxiv.2108.13871
openalex publication_date 2021/08/31 · openalex created_date 2022/10/04 · openalex updated_date 2026/07/28
Hard real-time systems like image processing, autonomous driving, etc. require an increasing need of computational power that classical multi-core platforms can not provide, to fulfill with their timing constraints. Heterogeneous Instruction Set Architecture (ISA) platforms allow accelerating real-time workloads on application-specific cores (e.g. GPU, DSP, ASICs) etc. and are suitable for these applications. In addition, these platforms provide larger design choices as a given functionnality can be implemented onto several types of compute elements. HPC-DAG (Heterogeneous Parallel Directed Acyclic Graph) task model has been recently proposed to capture real-time workload execution on heterogeneous platforms. It expresses the ISA heterogeneity, and some specific characteristics of hardware accelerators, as the absence of preemption or costly preemption, alternative implementations and on-line conditional execution. In this paper, we propose a time-table scheduling approach to allocate and schedule a set of HPC-DAG tasks onto a set of heterogeneous cores, by the mean Integer Linear Programming (ILP). Our design allows to handle heterogeniety of resources, on-line execution costs, and a faster solving time, by exploring gradually the design space