2020/05/28 by Pepe Vila, Andreas Abel, Vila, Pepe +7
Computer Science · Engineering · #Advanced Memory and Neural Computing #Cryptography and Security (cs.CR) #FOS: Computer and information sciences #Parallel Computing and Optimization Techniques #Security and Verification in Computing
paper · pdf · doi:10.48550/arxiv.2005.13853
openalex publication_date 2020/05/28 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Flushing the cache, using instructions like clflush and wbinvd, is commonly proposed as a countermeasure against access-based cache attacks. In this report, we show that several Intel caches, specifically the L1 caches in some pre-Skylake processors and the L2 caches in some post-Broadwell processors, leak information even after being flushed through clflush and wbinvd instructions. That is, security-critical assumptions about the behavior of clflush and wbinvd instructions are incorrect, and countermeasures that rely on them should be revised.