1987/01/01 by F. Masuoka, M. Momodom, Yoichi Iwata +1 · 3 citations
Computer Science · Engineering · #Advanced Data Storage Technologies #Algorithm #Cell structure #Cellular Automata and Applications #Charge trap flash #Computer hardware #Computer science #EEPROM #EPROM #Flash (photography) #Logic gate #NAND gate #Non-volatile memory #Physics #Semiconductor materials and devices
paper · doi:10.1109/iedm.1987.191485
openalex publication_date 1987/01/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/31
In order to realize ultra high density EPROM and Flash EEPROM, a NAND structure cell is proposed. This new structure is able to shrink cell size without scaling of device dimensions. The NAND structure cell realizes a cell as small as 6.43 µm2using 1.0 µm design rule. As a result, cell area per bit can be reduced by 30% compared with that of a 4M bit EPROM using the conventional structure and the same design rule. It is confirmed that each bit in a NAND cell is able to be programmed selectively. This high performance NAND structure cell is applicable to high density nonvolatile memories as large as 8M bit EPROM and Flash-EEPROM or beyond.