1999/01/01 by Michael Golden, S. Hesley, A. Scherer +11 · 1 citation
Computer Science · Engineering · #Central processing unit #Chip #Clock rate #Computer architecture #Computer hardware #Computer science #Debugging #Embedded Systems Design Techniques #Embedded system #Floating point #Instructions per cycle #Low-power high-performance VLSI design #Microarchitecture #Microprocessor #Operating system #Parallel Computing and Optimization Techniques #Parallel computing #Pipeline (software) #Software #x86
paper · doi:10.1109/4.799851
openalex publication_date 1999/01/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/06/26
An out-of-order, three-way superscalar /spl times/86 microprocessor with a 15-stage pipeline, organized to allow 600 MHz operation, can fetch, decode, and retire up to three /spl times/86 instructions per cycle to independent integer and floating-point schedulers. The schedulers can simultaneously dispatch up to nine operations to seven integer and three floating-point execution resources. A sophisticated, cell-based design technique and judicious application of custom circuitry permit the development of a processor with an aggressive architecture and high clock frequency with a rapid design cycle. Design-for-test techniques such as scan and clock bypassing permit straightforward testing and debugging of the part.