2021/07/24 by Guillermo Oyarzun, Oyarzun, Guillermo, Daniel Peyrolon +5
Computer Science · #Advanced Data Storage Technologies #Computational Physics (physics.comp-ph) #Distributed #Distributed and Parallel Computing Systems #FOS: Computer and information sciences #FOS: Physical sciences #Numerical Methods and Algorithms #Parallel #Parallel Computing and Optimization Techniques #and Cluster Computing (cs.DC)
paper · pdf · doi:10.48550/arxiv.2107.12371
openalex publication_date 2021/07/24 · openalex created_date 2022/07/25 · openalex updated_date 2026/07/28
Field Programmable Gate Arrays generate algorithmic specific architectures\nthat improve the code's FLOP per watt ratio. Such devices are re-gaining\ninterest due to the rise of new tools that facilitate their programming, such\nas OmpSs. The computational fluid dynamics community is always investigating\nnew architectures that can improve its algorithm's performance. Commonly, those\nalgorithms have a low arithmetic intensity and only reach a small percentage of\nthe peak performance. The sparse matrix-vector multiplication is one of the\nmost time-consuming operations on unstructured simulations. The matrix's\nsparsity pattern determines the indirect memory accesses of the multiplying\nvector. This data path is hard to predict, making traditional implementations\nfail. In this work, we present an FPGA architecture that maximizes the vector's\nre-usability by introducing a cache-like architecture. The cache is implemented\nas a circular list that maintains the BRAM vector components while needed.\nFollowing this strategy, up to 16 times of acceleration is obtained compared to\na naive implementation of the algorithm.\n